In arrays of closely spaced transistors, such as in DRAM memory arrays, it is known to form a self-aligned contact as illustrated in FIG. 1, in which two closely spaced transistors have an aperture formed in the area between them, which is also the location of a bitline buried in the substrate.
Sidewall spacers 35 (preferably oxide) isolate the contact from the two gates. It should be noted that there is a thick nitride cover 50 (illustratively 200 nm thick) over the gate stack that protects the gate during the etching process that forms the aperture for the contact. Unfortunately, this thick layer produces variation in linewidth across the chip that is unacceptable for high performance logic applications. The term high performance logic chips as used here means the transistor generation with very short gate length (on the order of 0.1 um Leff). These short gate length features on a logic chip require extremely precise control of physical dimensions and can tolerate only very small ACLV (across chip linewidth variation) to provide high performance, since the gate length has a direct effect on the current output of the transistor. The use of standard DRAM processing such as a thick nitride cap gate stack does not produce acceptable ACLV. In order to fulfill the ACLV requirement, standard logic process typically uses a simpler and thinner gate stack as seen in FIG. 2. With such a thinner gate stack, the variation on final gate length associated with processing is significantly smaller and able to satisfy the ACLV requirements.